Verilog on Fomu¶
“Hello world!” - Blink an LED¶
The canonical “Hello, world!” of hardware is to blink an LED. The
directory verilog-blink
contains a Verilog example of a blink
project. This takes the 48 MHz clock and divides it down by a large
number so you get an on/off pattern. It also exposes some of the signals
on the touchpads, making it possible to probe them with an oscilloscope.
Enter the verilog-blink
directory and build the verilog-blink
demo by using make
:
Make sure you set the ``FOMU_REV`` value to match your hardware! See the Required Hardware section.
make FOMU_REV=$FOMU_REV
You can load blink.bin
onto Fomu by using the same dfu-util -D
command we’ve been using. The LED should begin blinking on and off
regularly, indicating your bitstream was successfully loaded.
When writing HDL, a tool called
yosys
is used to convert the human readable verilog into a netlist representation, this is called synthesis. Once we have the netlist representation a tool callednextpnr
performs an operation called “place and route” which makes it something that will actually run on the FPGA. This is all done for you using theMakefile
in theverilog-blink
directory.A big feature of
nextpnr
over its predecessor, is the fact that it is timing-driven. This means that a design will be generated with a given clock domain guaranteed to perform fast enough.When the
make
command runsnextpnr-ice40
you will see the following included in the output;Max frequency for clock 'clk12': 24.63 MHz (PASS at 12.00 MHz) Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz) Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)This output example above shows we could run
clk12
at up to 24.63 MHz and it would still be stable, even though we only requested 12.00 MHz. Note that there is some variation between designs depending on how the placer and router decided to lay things out, so your exact frequency numbers might be different.